msm7500 series overclocking - G1 Android Development

crazybyte said:
I suggest to the rom cookers, to check about Qualcomm 7201A overclock, because in another forum, someone overclocked it to 768 mhz, and it seems to be true, because it's the real speed of the output of PLL generator. Our devices has a divisor.
Here is the link:
http://www.nuerom.com/BlogEngine/post/2009/09/06/Touch-Pro-running-at-800MHZ.aspx
I think that all the problem resides in the file:
http://android.git.kernel.org/?p=ke...3;hb=ebea985a6ec461a59afb86f0068cc1d79d7c8bf1
We think that the first step it's enable cpufreq to scale to 768mhz, and testing it in this freq.The info about scalling are in the lines 227 and 228:
227 CONFIG_MSM_CPU_FREQ_ONDEMAND_MAX=384000
228 CONFIG_MSM_CPU_FREQ_ONDEMAND_MIN=245760
Click to expand...
Click to collapse
i thought this might have better set up as its own thread.
edit
i have done some mild kernel work in winmo on a 7200 and do believe this is not only possible but a decent hack worth putting time into. also no2chem is to winmo as cyanogen is to android. so its from a good source

I posted in that thread too. I think the 65nm MSM7201A in the G1 could be easily pushed to 768MHz.
coolbho3000 said:
I was thinking about this but never could get any kernel to compile because I'm stupid. The other way would be to use PLL 2 to go all the way to 1056 (probably impossible ).
It's actually not that simple. This is the file you want to modify: http://android.git.kernel.org/?p=ke...13e3ef308591e8c0e5fe7ce0311d3f4d6b0b8;hb=HEAD
Add an entry for 768000 in static struct clkctl_acpu_speed acpu_freq_tbl[] for 768000.
{ 768000, ACPU_PLL_1, 1, 0, 128000, 5, VDD_7, 128000, 0, 5, -1 }
Those should be the correct values for 768MHz - all except for the last two 5 and -1. I don't know what those do, probably something to do with scaling.
Click to expand...
Click to collapse
Then add 768000 to static struct cpufreq_frequency_table freq_table[] and you should be able to echo those values into scaling_max_freq and scaling_min_freq

although this would kill the battery in 5 minuites it is great for hero and emulators as well

If someone could pull that off it would be killer.
Do you really think it would be that big of a drain on the battery if it was only climbing that high under heavy load situations rather than being set that high at all times?
I would be willing to take a hit in battery life to gain a performance increase of that type as long as the batter life doesn't end of 1/4 of what it was.

I've got an upgraded battery, so I don't care. Give me more speed!

One note please remember this was confirmed on 7500 not 7501a also it was a cdma phone not gsm but it could work with some work

If this makes a big different in performance, I'm willing to use the brick size battery I bought. It's been laying around unused since I bought it.

i am willing to try this but i dont know which file you edit. If someone can tell me ill give it a go

I don't think it'll be that easy though

You need to recompile the kernel with the added values in clkctl_acpu_speed acpu_freq_tbl[] in http://android.git.kernel.org...b0b8;hb=HEAD
I might give it a go if you want to try it out. I think we should determine if the last two 5 and -1 numbers are important first. Does look like scaling:
Code:
78 /* Index in acpu_freq_tbl[] for steppings. */
79 short down;
80 short up;
As far as I can tell the stepping values are used here:
Code:
332 while (cur_s != tgt_s) {
333 /*
334 * Always jump to target freq if within 256mhz, regulardless of
335 * PLL. If differnece is greater, use the predefinied
336 * steppings in the table.
337 */
338 int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz));
339 if (d > drv_state.max_speed_delta_khz) {
340 /* Step up or down depending on target vs current. */
341 int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ?
342 cur_s->up : cur_s->down;
343 if (clk_index < 0) { /* This should not happen. */
344 printk(KERN_ERR "cur:%u target: %u\n",
345 cur_s->a11clk_khz, tgt_s->a11clk_khz);
346 rc = -EINVAL;
347 goto out;
348 }
349 cur_s = &acpu_freq_tbl[clk_index];
350 } else {
351 cur_s = tgt_s;
352 }

daproy said:
You need to recompile the kernel with the added values in clkctl_acpu_speed acpu_freq_tbl[] in http://android.git.kernel.org...b0b8;hb=HEAD
I might give it a go if you want to try it out. I think we should determine if the last two 5 and -1 numbers are important first. Does look like scaling:
Code:
78 /* Index in acpu_freq_tbl[] for steppings. */
79 short down;
80 short up;
Click to expand...
Click to collapse
yep ill try it out if you compile it btw what is the worst hat could happen to my phone?

The code is optimized to stay on the same PLL so the last two numbers are the array index in the acpu_freq_tbl[] two go down to or up to from that entry. Since our new entry is ACPU_PLL_1 the next one down is entry 6 and there are none to step up to so it should be:
{ 768000, ACPU_PLL_1, 1, 0, 128000, 5, VDD_7, 128000, 0, 6, -1 }
The step up from 384000 should also be changed now that we're adding a higher frequency on the same PLL to:
{ 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, 8 }
So the acpu_freq_tbl[] should be:
Code:
static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 },
{ 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 },
{ 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 },
{ 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 },
{ 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 },
{ 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 },
{ 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, 8 },
{ 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 },
{ 768000, ACPU_PLL_1, 1, 0, 128000, [B]5[/B], VDD_7, 128000, 0, 6, -1 }
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
};
and
Code:
static struct cpufreq_frequency_table freq_table[] = {
{ 0, 19200 },
{ 1, 122880 },
{ 2, 128000 },
{ 3, 245760 },
{ 4, 384000 },
{ 5, 528000 },
{ 6, 768000 },
{ 7, CPUFREQ_TABLE_END },
};
coolbho3000, does this sound correct? You sure about the values for a11clk_src_div, ahbclk_khz, ahbclk_div at 768000? Sound like you've already started looking into this.
Is there a reason to change the AHB bus clock divider ahbclk_div to 5?

JJbdoggg, not sure what it'll do if it doesn't work. Probably freeze up the phone.

JJbdoggg said:
yep ill try it out if you compile it btw what is the worst hat could happen to my phone?
Click to expand...
Click to collapse
Your processor could get fried.

I'm 100% sure about a11clk_src_div (according to Qualcomm docs 0000 means you don't divide the PLL at all, leaving it at 768000, 0001 means you divide by 2, 0010 means you divide by 3, etc) but I'm not sure if ahbclk_khz is supposed to go above 132000 so I left it at 128000, making ahbclk_div 5 (768000/6 = 128000). Other possible values for the two might be 153600 and 4, and 192000 and 3. I'm digging through the Qualcomm documentation to see if I can find anything.

More info in a follow up from the original post:
http://www.nuerom.com/BlogEngine/post/2009/09/08/Yet-more-notes-on-overclocking.aspx

daproy said:
More info in a follow up from the original post:
http://www.nuerom.com/BlogEngine/post/2009/09/08/Yet-more-notes-on-overclocking.aspx
Click to expand...
Click to collapse
Seems unstable, but worth a shot. Seems like the worst that's happened to a WM user is a freeze.
3) There is a clock divider for the AHB that is separate from the ARM11 frequency. I’ve tried increasing the divider from the default of 0x4 to 0x5, with no real increase in stability.
It seems like multiple AHB clocks/dividers would work then, probably answering my above post... maybe best to try and see which is the most stable?

that would end getting really hot, if it is usable and perfected, hell yeah would i love to have some power like that out of my g1, i got 2 batteries

Well I played around with this a bit. Pulled cyanogen's latest kernel code with BFS from github. Patched acpuclock.c (patchfile attached). Compiled with the android toolchain.
First off there is definitely something wrong with the kernel i compiled because it was horrible slow to boot. I did use the .config from cyanogen 4.1.6 without edits so I'm not sure why. I can't imagine it was due to the patch since with default min and max scaling it should be running the same as the kernel compiled by cyanogen.
Regardless, I was able to try to overclocking:
Code:
# echo 528000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq
# echo 768000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# cat /proc/cpuinfo
Processor : ARMv6-compatible processor rev 2 (v6l)
BogoMIPS : 527.15
Features : swp half thumb fastmult edsp java
CPU implementer : 0x41
CPU architecture: 6TEJ
CPU variant : 0x1
CPU part : 0xb36
CPU revision : 2
Hardware : trout
Revision : 0080
Serial : 0000000000000000
# echo 768000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq
# cat /proc/cpuinfo
Processor : ARMv6-compatible processor rev 2 (v6l)
BogoMIPS : 766.77
Features : swp half thumb fastmult edsp java
CPU implementer : 0x41
CPU architecture: 6TEJ
CPU variant : 0x1
CPU part : 0xb36
CPU revision : 2
Hardware : trout
Revision : 0080
Serial : 0000000000000000
It reboot immediately following the cpuinfo but looks like it did scale up to 768000
Phone is fine after the reboot and back to default min max freq.
Before trying to toy around with different AHB clock dividers I should probably work out getting a good kernel to compile first, unless cyanogen has some spare time and feels like taking a look at this. I know I won't have any spare time in the next few days.

Amazing!!
Nice to see 766 in cpuinfo What do you think, was the reboot caused by cpu failure or "something wrong" in kernel?
If I understand well, we must modify kernel, and we cant easily install app to overclock..

Related

[Q] Editing CPU Freq tables - any info?

I am looking into modifying the kernel on the Incredible S (as HTC kindly dropped the sources) and I was wondering about changing the CPU Freq table. I can find lots of people who have done it, but very little info on how to go about it.
First of all there are two acpuclock files - one for the qsd8x5 and one for the 7x30. The phone has an 8255 so I presume the first is correct, but the buildprop is actually setup as if it contains a 7x30 so I am not sure which of the two files it is using.
Secondly, if there any reference as to what freq /voltages can be used for this chipset? Is it safe to just nick the table from a phone that already has this chip & an overclocked kernel? I have pasted the table from the 8x50 in case it is any help.
Code:
struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 19200, CCTL(CLK_TCXO, 1), SRC_RAW, 0, 0, 1050 },
{ 128000, CCTL(CLK_TCXO, 1), SRC_AXI, 0, 0, 1050 },
{ 245000, CCTL(CLK_MODEM_PLL, 1), SRC_RAW, 0, 0, 1050 },
{ 256000, CCTL(CLK_GLOBAL_PLL, 3), SRC_RAW, 0, 0, 1050 },
{ 384000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0A, 0, 1050 },
{ 422400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0B, 0, 1050 },
{ 460800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0C, 0, 1050 },
{ 499200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0D, 0, 1075 },
{ 537600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0E, 0, 1100 },
{ 576000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0F, 0, 1100 },
{ 614400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x10, 0, 1125 },
{ 652800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x11, 0, 1150 },
{ 691200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x12, 0, 1175 },
{ 729600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x13, 0, 1200 },
{ 768000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x14, 0, 1200 },
{ 806400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x15, 0, 1225 },
{ 844800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x16, 0, 1250 },
{ 883200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x17, 0, 1275 },
{ 921600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x18, 0, 1275 },
{ 960000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x19, 0, 1275 },
{ 998400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1A, 0, 1275 },
{ 0 },
};
Edit: I looked in the config and it looks like it's setup to use the 7x30 scropion chip which is very strange, but the cpu table does reveal some interesting info:
Code:
/* Use negative numbers for sources that can't be enabled/disabled */
#define SRC_LPXO (-2)
#define SRC_AXI (-1)
static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 24576, SRC_LPXO, 0, 0, 30720, 1000, VDD_RAW(1000) },
{ 61440, PLL_3, 5, 11, 61440, 1000, VDD_RAW(1000) },
{ 122880, PLL_3, 5, 5, 61440, 1000, VDD_RAW(1000) },
{ 184320, PLL_3, 5, 4, 61440, 1000, VDD_RAW(1000) },
{ MAX_AXI_KHZ, SRC_AXI, 1, 0, 61440, 1000, VDD_RAW(1000) },
{ 245760, PLL_3, 5, 2, 61440, 1000, VDD_RAW(1000) },
{ 368640, PLL_3, 5, 1, 122800, 1050, VDD_RAW(1050) },
{ 768000, PLL_1, 2, 0, 153600, 1100, VDD_RAW(1100) },
#ifndef CONFIG_ACPUCLOCK_LIMIT_768MHZ
/* ACPU >= 806.4MHz requires MSMC1 @ 1.2V. Voting for
* AXI @ 192MHz accomplishes this implicitly. 806.4MHz
* is updated to 1024MHz at runtime for QSD8x55. */
{ 806400, PLL_2, 3, 0, 192000, 1100, VDD_RAW(1100) },
#endif
{ 0 }
};
Anyone know where this would be updated at runtime?
I hate bumping my own thread, but I am really tearing my hair out over this one, does no one know?
You have any luck on this one?
According to specs it has a 1GHz cpu so it cannot use the freq table that only goes to 800MHz. So it has to be the first one.
Looks similar to the Desire freq table to try this one.
Code:
struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 19200, CCTL(CLK_TCXO, 1), SRC_RAW, 0, 0, 1050 },
{ 128000, CCTL(CLK_TCXO, 1), SRC_AXI, 0, 0, 1050 },
{ 245000, CCTL(CLK_MODEM_PLL, 1), SRC_RAW, 0, 0, 1050 },
{ 256000, CCTL(CLK_GLOBAL_PLL, 3), SRC_RAW, 0, 0, 1050 },
{ 384000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0A, 0, 1050 },
{ 422400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0B, 0, 1050 },
{ 460800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0C, 0, 1050 },
{ 499200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0D, 0, 1075 },
{ 537600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0E, 0, 1100 },
{ 576000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0F, 0, 1100 },
{ 614400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x10, 0, 1125 },
{ 652800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x11, 0, 1150 },
{ 691200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x12, 0, 1175 },
{ 729600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x13, 0, 1200 },
{ 768000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x14, 0, 1200 },
{ 806400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x15, 0, 1225 },
{ 844800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x16, 0, 1250 },
{ 883200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x17, 0, 1275 },
{ 921600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x18, 0, 1275 },
{ 960000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x19, 0, 1275 },
{ 998400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1A, 0, 1275 },
{ 1036800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1B, 0, 1275 },
{ 1075200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1C, 0, 1275 },
{ 1113600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1275 },
{ 0 },
};
Here's some inspiration: https://github.com/thalamus/kernel/blob/2.6.35.14-bravo/arch/arm/mach-msm/acpuclock-qsd8x50.c

[KERNEL][Sep18]-=UNITY V9=-[2.6.35.14][OC/UV][CIFS/TUN][SLQB][NOOP][2WCR]

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Features:
Based on Official GB kernel source code from HTC
Patched to .14
2-way call records - https://market.android.com/details?id=com.skvalex.callrecorder
OC up to 2016MHz (Default 245 - 1075MHz @ Ondemand)
VDD sysfs interface
Tweaked Interactive governor
Additional Virtuous/SmartAss/SavagedZen/Scary governors
Audio Boosts (20%)
CIFS
TUN
CFS
SLQB
NOOP I/O scheduler
TINY PREEMPT RCU
Full EXT4 Support
and more...
Click to expand...
Click to collapse
Compatible with:
All Sense ROM's based on Android 2.3.4 - 2.3.5 >
Click to expand...
Click to collapse
Issues:
- you tell me
Click to expand...
Click to collapse
Install:
- Flash via CWM
Click to expand...
Click to collapse
Download UNITY V9:
http://www.multiupload.com/VPFKEN5RAM
For correct work 2wcr function use CallRecorder app https://market.android.com/details?id=com.skvalex.callrecorder
Click to expand...
Click to collapse
Enjoy
Click to expand...
Click to collapse
More info & GPL:
Virtuous Home: http://www.virtuousrom.com
Virtuous Forum: http://forums.virtuousrom.com/index.php
HTC: http://www.htc.com/
Kernel GIT: https://github.com/mdeejay/msm7x30-gb-kernel
Thanks: Markinus (for teach), avs234 & skvalex (for 2WCR), Flemmard, seo and other Virtuous team, LordClockaN, LeeDroid, etc​
Changelog:
Code:
UNITY V9:
- OC up to 2.0GHz
- Tweak all governors
- New Virtuous governor
- XZ compressing
- PREEMPT_TINY_RCU
- lots minor fixes & tweaks
UNITY V8:
- Fixed VDD
- OC up to 1804MHz
UNITY V7:
- Added VDD sysfs interface
UNITY V6:
- Enabled AMR format support for CallRecorder
- Fixed support apps like "Voice Commander"
UNITY V5:
- Fixed USB for Android 2.3.4
- "Fast USB charging" hack
UNITY V4:
- Added new module for 2wcr
---- Fixed hardware amr recordings
---- Fixed stereo recordings
---- Fixed missing call recordings
- Added SavagedZen governor
- Added Scary governor
- Some minor cleanups
UNITY V3:
- New OC method with 50 steps
- New acpu table
- Fixed kernel info
- Some cleanups
UNITY V2:
- Reverted new audio drivers
- Added 2WCR patch for new audio drivers
- Added Wi-Fi Calling support for T-Mobile users (Kineto GAN)
- Disabled BFQ / Enabled Deadline
- Disabled btrfs & ext2 support
UNITY V1:
- Added support HTC Desire Z & HTC My Touch 4G
- Tweaked video drivers
- CIFS/TUN/UTF set as modules
[SIZE="2"]v.23:
- Back to old video drivers (from official HTC source)
- ACPU edits
v.22:
- Improved SmartAss works with >=1600Mhz
v.21:
- new acpu table
- tweaked governors
- some cleanups
- max OC 1708MHz
v.20:
- not released
v.19:
- Updated video drivers from CodeAurora
- Added BFQ v.2-r1
- Tweak SmartAss (XBOCT)
- Increase GPU & Camera memory allocation (Lee)
- Disable write cache support
- Correct LCD panel size
- Added 1612MHz to acpu table
v.18:
- Added 2 steps in acpu table
- New universal updater script for both filesystems
- Prevent memory leak on hotplug
v.17:
- Added 2-way call records
v.16:
- Based on official GB kernel source code from HTC
- Enabled OC (1516MHz MAX)
- Removed 2-way call records patch
- Added Smartass governor
- Added interactive governor
- Added Conservative governor
- Added audio boost
- Added default V(R) I/O Scheduler
- Added default SLQB Memory allocator[/SIZE]
ACPU Table:
Code:
{ 122000, PLL_3, 5, 2, 61440, 875, VDD_RAW(875) },
{ 245000, PLL_3, 5, 1, 192000, 875, VDD_RAW(875) },
{ 307200, PLL_3, 5, 1, 192000, 900, VDD_RAW(900) },
{ 384000, PLL_1, 2, 0, 192000, 900, VDD_RAW(900) },
{ 460800, PLL_3, 5, 1, 192000, 925, VDD_RAW(925) },
{ 537600, PLL_2, 3, 0, 192000, 950, VDD_RAW(950) },
{ 614400, PLL_2, 3, 0, 192000, 950, VDD_RAW(950) },
{ 691200, PLL_2, 3, 0, 192000, 975, VDD_RAW(975) },
{ 768000, PLL_2, 3, 0, 192000, 1000, VDD_RAW(1000) },
{ 844800, PLL_2, 3, 0, 192000, 1000, VDD_RAW(1000) },
{ 921600, PLL_2, 3, 0, 192000, 1025, VDD_RAW(1025) },
{ 998400, PLL_2, 3, 0, 192000, 1025, VDD_RAW(1025) },
{ 1075200, PLL_2, 3, 0, 192000, 1050, VDD_RAW(1050) },
{ 1152000, PLL_2, 3, 0, 192000, 1075, VDD_RAW(1075) },
{ 1228800, PLL_2, 3, 0, 192000, 1100, VDD_RAW(1100) },
{ 1305600, PLL_2, 3, 0, 192000, 1125, VDD_RAW(1125) },
{ 1382400, PLL_2, 3, 0, 192000, 1150, VDD_RAW(1150) },
{ 1459200, PLL_2, 3, 0, 192000, 1200, VDD_RAW(1200) },
{ 1536000, PLL_2, 3, 0, 192000, 1275, VDD_RAW(1275) },
{ 1612800, PLL_2, 3, 0, 199680, 1325, VDD_RAW(1325) },
{ 1689600, PLL_2, 3, 0, 199680, 1375, VDD_RAW(1375) },
{ 1766400, PLL_2, 3, 0, 199680, 1425, VDD_RAW(1425) },
{ 1843200, PLL_2, 3, 0, 199680, 1450, VDD_RAW(1450) },
{ 1920000, PLL_2, 3, 0, 199680, 1475, VDD_RAW(1475) },
{ 1996800, PLL_2, 3, 0, 199680, 1500, VDD_RAW(1500) },
{ 2016000, PLL_2, 3, 0, 201600, 1500, VDD_RAW(1500) },
Beta versions:
Code:
Download:
Woow!
It's uv? Which governator??
Can you give us more details?
Thanks!
Sent from future
NICE!!
So you succeded!!
Congrats!!
Is this the first costume kernel for a gingerbread Desire HD? If so, can it be flashed to another 2.3.3 ROM (Capy's rom)?
ALso, m-deejay, can you post the RUU which this is based on.
Well I don't believe it. Well done good sir. Well done!
That's really nice News!!
Oh! Great news. U did that. U proved your self as MDJ once again. Thank you!
Just download, trying it now. Report u back!
I feel its better to do a nand back up first
Sent from my Desire HD
may be some issues in kernel. need more tests
Has the source been released then? I thought this wasn't possible until HTC released the gingerbread source?
Well done anyway. I used your kernals and roms when I had my HD2 so will give this a go.
dowlinr said:
Has the source been released then? I thought this wasn't possible until HTC released the gingerbread source?
Well done anyway. I used your kernals and roms when I had my HD2 so will give this a go.
Click to expand...
Click to collapse
HTC Incredible S source
The first 2.3.3 sense cusomize kernel!Thanks for the great work...Hopefully it can have improve the battery life..
m-deejay said:
Changelog:
Code:
v.1:
- Initial Release
Click to expand...
Click to collapse
Thank you so much, been waiting for this all day
Sent from my Desire HD using Tapatalk
And you get the bragging rights of having the first custom kernel for 2.3 sense.
Sense kernels, Sense ROM's, CM ROM's, is there anything you can't do? Got yourself a fan for life here.
work with coredroid thanks 5.4
man, you are awsome
6 stars
it works with Spike_M's DS port v1
to all
please test all functions of your phone with kernel
m-deejay said:
to all
please test all functions of your phone with kernel
Click to expand...
Click to collapse
Just flashed on CoreDroid5.4
Seems everything working. Quadrant score was 1950 @ 1401mhz with interactive governor and 1810 with performance. Confused..!
Feels good so far..
Edit: Bluetooth isn't working properly. Not detecting my SE Bluetooth stereo headset, even its already paired. Hope u can check this. No issues with WiFi
Sorry to say, need to look at Mobile data too.
Sent from my Desire HD
There seems to be a problem playing video...from the gallery and also YouTube.
I was checking YT and a few videos i`d taken earlier and they worked before flashing the kernel.
Running CD 5.4

[Q] Kernel Modules

Hello! I am currently trying to compile my own kernel with Smartass governor and Higher CPU frequencies for my MyTouch 4G Slide. I successfully compiled my own kernel from the HTC Source but now have ran into a problem... I am trying to compile my own Smartass module from the source I found Here but unfortunately this being my first kernel I have no idea how... Whenever I try to compile the module gives me an error..
Im guessing its related to the line
"#define OFS_KALLSYMS_LOOKUP_NAME 0xc009684c // kallsyms_lookup_name"
but not sure... How would I find this address? How do I incorporate the governor after I compile the module successfully?
Thanks in advanced!
~GiGoO
gigoo25 said:
Hello! I am currently trying to compile my own kernel with Smartass governor and Higher CPU frequencies for my MyTouch 4G Slide. I successfully compiled my own kernel from the HTC Source but now have ran into a problem... I am trying to compile my own Smartass module from the source I found Here but unfortunately this being my first kernel I have no idea how... Whenever I try to compile the module gives me an error..
Im guessing its related to the line
"#define OFS_KALLSYMS_LOOKUP_NAME 0xc009684c // kallsyms_lookup_name"
but not sure... How would I find this address? How do I incorporate the governor after I compile the module successfully?
Thanks in advanced!
~GiGoO
Click to expand...
Click to collapse
Okay, the advice I am going to give you is contrary to what you hear about working on kernels - I am going to tell you not to try to make a new module, but to edit the source directly.
in .../arch/arm/mach-msm/acpuclock-8x60.c you will find the primary cpu table for clock speed.
You will notice here and elsewhere scattered throughout the kernel source that HTC made a mess of things - they originally had programmed the kernel to support the chip to it's rated speed of 1.5...and then somewhere along the way changed their minds and brought it down to 1.2.
Now we have scattered references to the 1.5 clock speed throughout kernel source, and so in order to mess with clock speed directly you will need to clean up these leftovers we have floating around.
In the file I mentioned above, you can get your start - but instead of trying to add a module to the kernel it's better in this case to work with it directly.
If someone gets a clean version of the code set and ready for us that we could build from, then maybe adding modules would be more successful - as it's technically the correct way to do what you are trying.
You happen to be working on exactly the same thing I am working on right this very minute, so that's fortunate in regards to your question I suppose. I'm glad to see someone else putting time into kernel work for this device.
Hope this helps you out, even though it's not what you want to hear.
Blue6IX said:
Okay, the advice I am going to give you is contrary to what you hear about working on kernels - I am going to tell you not to try to make a new module, but to edit the source directly.
in .../arch/arm/mach-msm/acpuclock-8x60.c you will find the primary cpu table for clock speed.
You will notice here and elsewhere scattered throughout the kernel source that HTC made a mess of things - they originally had programmed the kernel to support the chip to it's rated speed of 1.5...and then somewhere along the way changed their minds and brought it down to 1.2.
Now we have scattered references to the 1.5 clock speed throughout kernel source, and so in order to mess with clock speed directly you will need to clean up these leftovers we have floating around.
In the file I mentioned above, you can get your start - but instead of trying to add a module to the kernel it's better in this case to work with it directly.
If someone gets a clean version of the code set and ready for us that we could build from, then maybe adding modules would be more successful - as it's technically the correct way to do what you are trying.
You happen to be working on exactly the same thing I am working on right this very minute, so that's fortunate in regards to your question I suppose. I'm glad to see someone else putting time into kernel work for this device.
Hope this helps you out, even though it's not what you want to hear.
Click to expand...
Click to collapse
Thanks for the quick reply!
So in order to add more frequencies you would have to edit "acpuclock-8x60.c" and what some other files in the same directory correct?
Yea, i've been digging through kernel source for a while now, but only off and on - i'm just now starting to focus more attention on it. I don't think i've isolated everywhere the clock speed is defined, but that cpu table is the primary reference point.
Sent from my NookColor using xda premium
Just out of curiosity, what about acpuclock-arm11.c in the same folder?
blackknightavalon said:
Just out of curiosity, what about acpuclock-arm11.c in the same folder?
Click to expand...
Click to collapse
Shouldn't have any effect. Arm11 architecture topped out at 1Ghz I believe, single core only.
A bit of a dated product specification, considering we are running over 1Ghz and dual core.
Edit:
Ever seen the movie hackers? (lol...as if I have to ask) remeber when they are in burns bedroom and they are talking about risc architecture, and how it will change everything?
(reduced instruction set computing)
Well, they were right - and when the ARM-7 series of processors hit it had about the same effect on the portable digital world. They worked their way up to ARM-9 then 11, but I think that was the end of the ARM line, at least as much as I remember reading up on.
1 Ghz is basically ancient tech in today's world.
My guess is your both working on a sense/mysense 3.0 kernel....once you get that how hard would it be to upgrade to sense 3.5 compatibility?
To be flat-out honest with you, I have no idea.
I don't know what the difference is. Being a newcomer to Android, and not knowing what Sense was before purchasing this device at the beginning of august, i'm still learning about it all.
I suppose that may surprise some people to learn, but I don't BS around with pretending to know more then I do. That only leads to not learning what I should, and spreading false or inaccurate information. There are a lot of posts around here I want to respond to but can't for lack of information, and even spending literally around the clock learning Android there is a whole lot I haven't yet.
I can work with what's right in front of me and in my hand, reverse engineer it and take it apart to tinker and find out how it works, but if I don't have it it's outside of my sphere of learning at the moment.
If you could expand on the technical details and differences between 3.0 and 3.5 I could give you a better answer.
Blue6IX said:
To be flat-out honest with you, I have no idea.
I don't know what the difference is. Being a newcomer to Android, and not knowing what Sense was before purchasing this device at the beginning of august, i'm still learning about it all.
I suppose that may surprise some people to learn, but I don't BS around with pretending to know more then I do. That only leads to not learning what I should, and spreading false or inaccurate information. There are a lot of posts around here I want to respond to but can't for lack of information, and even spending literally around the clock learning Android there is a whole lot I haven't yet.
I can work with what's right in front of me and in my hand, reverse engineer it and take it apart to tinker and find out how it works, but if I don't have it it's outside of my sphere of learning at the moment.
If you could expand on the technical details and differences between 3.0 and 3.5 I could give you a better answer.
Click to expand...
Click to collapse
IN all actuality I don't believe there is a whole big difference between the two...basically more visual....cleaned up improvements to Sense 3.0....my guess is when HTC releases a phone with ICS it might even have a whole new sense release...but 3.5 is so new....hard to tell....there is only a few phones out with 3.5...where are you learning your coding from...I can try and learn..i have very minimal python coding experience so would be like learning Chinese I imagine...I excel more on beta testing...i can take something and run it hard through paces...coding....not so much....I am an inside the box kind of thinker...lol
beezie916 said:
IN all actuality I don't believe there is a whole big difference between the two...basically more visual....cleaned up improvements to Sense 3.0....my guess is when HTC releases a phone with ICS it might even have a whole new sense release...but 3.5 is so new....hard to tell....there is only a few phones out with 3.5...where are you learning your coding from...I can try and learn..i have very minimal python coding experience so would be like learning Chinese I imagine...I excel more on beta testing...i can take something and run it hard through paces...coding....not so much....I am an inside the box kind of thinker...lol
Click to expand...
Click to collapse
a lifetime of tinkering with stuff on computers, everything i've learned about Android has been right here at XDA.
The best place to start learning to code is learn HTML. Yea - that's it right there.
If you can learn HTML, you can learn any human-readable programming language.
If you want to learn to make Android apps, you need to know java. If you want to learn to code kernels, you need to learn C flavor languages.
After you play with a few higher level programming languages you learn they are all the same - the only difference is syntax.
Blue6IX said:
a lifetime of tinkering with stuff on computers, everything i've learned about Android has been right here at XDA.
The best place to start learning to code is learn HTML. Yea - that's it right there.
If you can learn HTML, you can learn any human-readable programming language.
If you want to learn to make Android apps, you need to know java. If you want to learn to code kernels, you need to learn C flavor languages.
After you play with a few higher level programming languages you learn they are all the same - the only difference is syntax.
Click to expand...
Click to collapse
Well I have been messing around with it and ended up editing "acpuclock-8x60" here is the final product...
Code:
/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/cpufreq.h>
#include <linux/cpu.h>
#include <linux/regulator/consumer.h>
#include <asm/cpu.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
#include <mach/msm_bus.h>
#include <mach/msm_bus_board.h>
#include <mach/socinfo.h>
#include "acpuclock.h"
#include "clock-8x60.h"
#include "rpm-regulator.h"
#include "avs.h"
#define dprintk(msg...) \
cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-msm", msg)
/* Frequency switch modes. */
#define SHOT_SWITCH 4
#define HOP_SWITCH 5
#define SIMPLE_SLEW 6
#define COMPLEX_SLEW 7
/* PLL calibration limits.
* The PLL hardware is capable of 384MHz to 1536MHz. The L_VALs
* used for calibration should respect these limits. */
#define L_VAL_SCPLL_CAL_MIN 0x08 /* = 432 MHz with 27MHz source */
#define L_VAL_SCPLL_CAL_MAX 0x1C /* = 1512 MHz with 27MHz source */
#define MAX_VDD_SC 1250000 /* uV */
#define MAX_AXI 310500 /* KHz */
#define SCPLL_LOW_VDD_FMAX 594000 /* KHz */
#define SCPLL_LOW_VDD 1000000 /* uV */
#define SCPLL_NOMINAL_VDD 1100000 /* uV */
/* SCPLL Modes. */
#define SCPLL_POWER_DOWN 0
#define SCPLL_BYPASS 1
#define SCPLL_STANDBY 2
#define SCPLL_FULL_CAL 4
#define SCPLL_HALF_CAL 5
#define SCPLL_STEP_CAL 6
#define SCPLL_NORMAL 7
#define SCPLL_DEBUG_NONE 0
#define SCPLL_DEBUG_FULL 3
/* SCPLL registers offsets. */
#define SCPLL_DEBUG_OFFSET 0x0
#define SCPLL_CTL_OFFSET 0x4
#define SCPLL_CAL_OFFSET 0x8
#define SCPLL_STATUS_OFFSET 0x10
#define SCPLL_CFG_OFFSET 0x1C
#define SCPLL_FSM_CTL_EXT_OFFSET 0x24
#define SCPLL_LUT_A_HW_MAX (0x38 + ((L_VAL_SCPLL_CAL_MAX / 4) * 4))
/* Clock registers. */
#define SPSS0_CLK_CTL_ADDR (MSM_ACC0_BASE + 0x04)
#define SPSS0_CLK_SEL_ADDR (MSM_ACC0_BASE + 0x08)
#define SPSS1_CLK_CTL_ADDR (MSM_ACC1_BASE + 0x04)
#define SPSS1_CLK_SEL_ADDR (MSM_ACC1_BASE + 0x08)
#define SPSS_L2_CLK_SEL_ADDR (MSM_GCC_BASE + 0x38)
/* Speed bin register. */
#define QFPROM_SPEED_BIN_ADDR (MSM_QFPROM_BASE + 0x00C0)
static const void * const clk_ctl_addr[] = {SPSS0_CLK_CTL_ADDR,
SPSS1_CLK_CTL_ADDR};
static const void * const clk_sel_addr[] = {SPSS0_CLK_SEL_ADDR,
SPSS1_CLK_SEL_ADDR, SPSS_L2_CLK_SEL_ADDR};
static const int rpm_vreg_voter[] = { RPM_VREG_VOTER1, RPM_VREG_VOTER2 };
static struct regulator *regulator_sc[NR_CPUS];
enum scplls {
CPU0 = 0,
CPU1,
L2,
};
static const void * const sc_pll_base[] = {
[CPU0] = MSM_SCPLL_BASE + 0x200,
[CPU1] = MSM_SCPLL_BASE + 0x300,
[L2] = MSM_SCPLL_BASE + 0x400,
};
enum sc_src {
ACPU_AFAB,
ACPU_PLL_8,
ACPU_SCPLL,
};
static struct clock_state {
struct clkctl_acpu_speed *current_speed[NR_CPUS];
struct clkctl_l2_speed *current_l2_speed;
spinlock_t l2_lock;
struct mutex lock;
uint32_t acpu_switch_time_us;
uint32_t vdd_switch_time_us;
uint32_t max_speed_delta_khz;
} drv_state;
struct clkctl_l2_speed {
unsigned int khz;
unsigned int src_sel;
unsigned int l_val;
unsigned int vdd_dig;
unsigned int vdd_mem;
unsigned int bw_level;
};
static struct clkctl_l2_speed *l2_vote[NR_CPUS];
struct clkctl_acpu_speed {
unsigned int use_for_scaling[2]; /* One for each CPU. */
unsigned int acpuclk_khz;
int pll;
unsigned int acpuclk_src_sel;
unsigned int acpuclk_src_div;
unsigned int core_src_sel;
unsigned int l_val;
struct clkctl_l2_speed *l2_level;
unsigned int vdd_sc;
unsigned int avsdscr_setting;
};
/* Instantaneous bandwidth requests in MB/s. */
#define BW_MBPS(_bw) \
{ \
.vectors = &(struct msm_bus_vectors){ \
.src = MSM_BUS_MASTER_AMPSS_M0, \
.dst = MSM_BUS_SLAVE_EBI_CH0, \
.ib = (_bw) * 1000000UL, \
.ab = 0, \
}, \
.num_paths = 1, \
}
static struct msm_bus_paths bw_level_tbl[] = {
[0] = BW_MBPS(824), /* At least 103 MHz on bus. */
[1] = BW_MBPS(1336), /* At least 167 MHz on bus. */
[2] = BW_MBPS(2008), /* At least 251 MHz on bus. */
[3] = BW_MBPS(2480), /* At least 310 MHz on bus. */
};
static struct msm_bus_scale_pdata bus_client_pdata = {
.usecase = bw_level_tbl,
.num_usecases = ARRAY_SIZE(bw_level_tbl),
.active_only = 1,
.name = "acpuclock",
};
static uint32_t bus_perf_client;
/* L2 frequencies = 2 * 27 MHz * L_VAL */
static struct clkctl_l2_speed l2_freq_tbl_v2[] = {
[0] = { MAX_AXI, 0, 0, 1000000, 1100000, 0},
[1] = { 245760, 1, 0x09, 1000000, 1100000, 0},
[2] = { 368640, 1, 0x0A, 1000000, 1100000, 0},
[3] = { 768000, 1, 0x0B, 1100000, 1100000, 0},
[4] = { 806400, 1, 0x0C, 1100000, 1100000, 0},
[5] = { 825600, 1, 0x0D, 1100000, 1100000, 0},
[6] = { 844800, 1, 0x0E, 1100000, 1100000, 1},
[7] = { 864000, 1, 0x0F, 1100000, 1100000, 1},
[8] = { 883200, 1, 0x10, 1100000, 1100000, 1},
[9] = { 902400, 1, 0x11, 1100000, 1100000, 1},
[10] = { 921600, 1, 0x12, 1100000, 1100000, 1},
[11] = { 940800, 1, 0x13, 1100000, 1100000, 2},
[12] = { 960000, 1, 0x14, 1100000, 1100000, 2},
[13] = { 979200, 1, 0x15, 1100000, 1100000, 2},
[14] = { 998400, 1, 0x16, 1100000, 1100000, 2},
[15] = {1017600, 1, 0X1A, 1100000, 1100000, 2},
[16] = {1036800, 1, 0x1B, 1100000, 1200000, 3},
[17] = {1056000, 1, 0x1C, 1100000, 1200000, 3},
[18] = {1075200, 1, 0x1D, 1100000, 1200000, 3},
[19] = {1094400, 1, 0x1E, 1100000, 1200000, 3},
[20] = {1209600, 1, 0x1F, 1100000, 1200000, 3},
[21] = {1248000, 1, 0x20, 1100000, 1200000, 4},
[22] = {1267200, 1, 0x21, 1100000, 1200000, 4},
[23] = {1286400, 1, 0x22, 1100000, 1200000, 4},
[24] = {1305600, 1, 0x23, 1100000, 1200000, 4},
[25] = {1344000, 1, 0x24, 1100000, 1200000, 4},
[26] = {1363200, 1, 0x25, 1100000, 1200000, 5},
[27] = {1382400, 1, 0x26, 1200000, 1200000, 5},
[28] = {1401600, 1, 0x2A, 1200000, 1250000, 5},
[29] = {1459200, 1, 0x2B, 1200000, 1250000, 5},
[30] = {1512000, 1, 0x2C, 1250000, 1250000, 5},
};
#define L2(x) (&l2_freq_tbl_v2[(x)])
/* SCPLL frequencies = 2 * 27 MHz * L_VAL */
static struct clkctl_acpu_speed acpu_freq_tbl_v2[] = {
{ {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 812500, 0x03006000},
/* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */
{ {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 812500, 0x03006000},
{ {1, 1}, 245760, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 850000, 0x03006000},
{ {1, 1}, 368640, ACPU_SCPLL, 0, 0, 0, 0x09, L2(2), 875000, 0x03006000},
{ {1, 1}, 768000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 975000, 0x03006000},
{ {1, 1}, 806400, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 975000, 0x03006000},
{ {1, 1}, 825600, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 1032500, 0x03006000},
{ {1, 1}, 844800, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 1035000, 0x03006000},
{ {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 1037500, 0x03006000},
{ {1, 1}, 883200, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 1042500, 0x03006000},
{ {1, 1}, 902400, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 1060000, 0x03006000},
{ {1, 1}, 921600, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 1062500, 0x03006000},
{ {1, 1}, 940800, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 1065000, 0x03006000},
{ {1, 1}, 960000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 1067500, 0x03006000},
{ {1, 1}, 979200, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1087500, 0x03006000},
{ {1, 1}, 998400, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1100000, 0x03006000},
{ {1, 1}, 1017600, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1125000, 0x03006000},
{ {1, 1}, 1036800, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(16), 1125000, 0x03006000},
{ {1, 1}, 1056000, ACPU_SCPLL, 0, 0, 1, 0x1B, L2(17), 1150000, 0x03006000},
{ {1, 1}, 1075200, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(18), 1135000, 0x03006000},
{ {1, 1}, 1094400, ACPU_SCPLL, 0, 0, 1, 0x1D, L2(19), 1137500, 0x03006000},
{ {1, 1}, 1209600, ACPU_SCPLL, 0, 0, 1, 0x1E, L2(20), 1190000, 0x03006000},
{ {1, 1}, 1248000, ACPU_SCPLL, 0, 0, 1, 0x20, L2(21), 1195000, 0x03006000},
{ {1, 1}, 1267200, ACPU_SCPLL, 0, 0, 1, 0x21, L2(22), 1195000, 0x03006000},
{ {1, 1}, 1286400, ACPU_SCPLL, 0, 0, 1, 0x22, L2(23), 1195000, 0x03006000},
{ {1, 1}, 1305600, ACPU_SCPLL, 0, 0, 1, 0x23, L2(24), 1195000, 0x03006000},
{ {1, 1}, 1344000, ACPU_SCPLL, 0, 0, 1, 0x25, L2(25), 1195000, 0x03006000},
{ {1, 1}, 1363200, ACPU_SCPLL, 0, 0, 1, 0x26, L2(26), 1197500, 0x03006000},
{ {1, 1}, 1382400, ACPU_SCPLL, 0, 0, 1, 0x2A, L2(27), 1200000, 0x03006000},
{ {1, 1}, 1401600, ACPU_SCPLL, 0, 0, 1, 0x2B, L2(28), 1225000, 0x03006000},
{ {1, 1}, 1459200, ACPU_SCPLL, 0, 0, 1, 0x2C, L2(29), 1225000, 0x03006000},
{ {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x2D, L2(30), 1250000, 0x03006000},
{ {0, 0}, 0 },
};
/* acpu_freq_tbl row to use when reconfiguring SC/L2 PLLs. */
#define CAL_IDX 1
static struct clkctl_acpu_speed *acpu_freq_tbl;
static struct clkctl_l2_speed *l2_freq_tbl;
static unsigned int l2_freq_tbl_size;
unsigned long acpuclk_get_rate(int cpu)
{
return drv_state.current_speed[cpu]->acpuclk_khz;
}
uint32_t acpuclk_get_switch_time(void)
{
return drv_state.acpu_switch_time_us;
}
unsigned long clk_get_max_axi_khz(void)
{
return MAX_AXI;
}
EXPORT_SYMBOL(clk_get_max_axi_khz);
#define POWER_COLLAPSE_KHZ MAX_AXI
unsigned long acpuclk_power_collapse(void)
{
int ret = acpuclk_get_rate(smp_processor_id());
acpuclk_set_rate(smp_processor_id(), POWER_COLLAPSE_KHZ, SETRATE_PC);
return ret;
}
#define WAIT_FOR_IRQ_KHZ MAX_AXI
unsigned long acpuclk_wait_for_irq(void)
{
int ret = acpuclk_get_rate(smp_processor_id());
acpuclk_set_rate(smp_processor_id(), WAIT_FOR_IRQ_KHZ, SETRATE_SWFI);
return ret;
}
static void select_core_source(unsigned int id, unsigned int src)
{
uint32_t regval;
int shift;
shift = (id == L2) ? 0 : 1;
regval = readl(clk_sel_addr[id]);
regval &= ~(0x3 << shift);
regval |= (src << shift);
writel(regval, clk_sel_addr[id]);
}
static void select_clk_source_div(unsigned int id, struct clkctl_acpu_speed *s)
{
uint32_t reg_clksel, reg_clkctl, src_sel;
/* Configure the PLL divider mux if we plan to use it. */
if (s->core_src_sel == 0) {
reg_clksel = readl(clk_sel_addr[id]);
/* CLK_SEL_SRC1N0 (bank) bit. */
src_sel = reg_clksel & 1;
/* Program clock source and divider. */
reg_clkctl = readl(clk_ctl_addr[id]);
reg_clkctl &= ~(0xFF << (8 * src_sel));
reg_clkctl |= s->acpuclk_src_sel << (4 + 8 * src_sel);
reg_clkctl |= s->acpuclk_src_div << (0 + 8 * src_sel);
writel(reg_clkctl, clk_ctl_addr[id]);
/* Toggle clock source. */
reg_clksel ^= 1;
/* Program clock source selection. */
writel(reg_clksel, clk_sel_addr[id]);
}
}
static void scpll_enable(int sc_pll, uint32_t l_val)
{
uint32_t regval;
/* Power-up SCPLL into standby mode. */
writel(SCPLL_STANDBY, sc_pll_base[sc_pll] + SCPLL_CTL_OFFSET);
dsb();
udelay(10);
/* Shot-switch to target frequency. */
regval = (l_val << 3) | SHOT_SWITCH;
writel(regval, sc_pll_base[sc_pll] + SCPLL_FSM_CTL_EXT_OFFSET);
writel(SCPLL_NORMAL, sc_pll_base[sc_pll] + SCPLL_CTL_OFFSET);
dsb();
udelay(20);
}
static void scpll_check_ico(int sc_pll)
{
uint32_t regval;
regval = readl(sc_pll_base[sc_pll] + SCPLL_CTL_OFFSET);
if (regval & BIT(18)) {
dprintk("SCPLL%d: ICO2 set before scpll_disable. Register=%d\n",
sc_pll, regval);
}
}
static void scpll_disable(int sc_pll)
{
scpll_check_ico(sc_pll);
/* Power down SCPLL. */
writel(SCPLL_POWER_DOWN, sc_pll_base[sc_pll] + SCPLL_CTL_OFFSET);
}
#ifdef CONFIG_ACPUCLK_SET_RATE_DEBUG
#define SETRATE_TIMEOUT (3 * HZ)
struct task_struct *set_rate_process;
static void set_rate_timeout_handler(unsigned long data)
{
struct task_struct *g, *p;
pr_info("acpuclk_set_rate timeout, print stack\n");
read_lock(&tasklist_lock);
do_each_thread(g, p) {
if (p == set_rate_process )
sched_show_task(set_rate_process);
} while_each_thread(g, p);
read_unlock(&tasklist_lock);
pr_info("Blocked tasks\n");
show_state_filter(TASK_UNINTERRUPTIBLE);
}
static DEFINE_TIMER(set_rate_timer, set_rate_timeout_handler, 0, 0);
#endif
static void scpll_change_freq(int sc_pll, uint32_t l_val)
{
uint32_t regval;
const void *base_addr = sc_pll_base[sc_pll];
/* Complex-slew switch to target frequency. */
regval = (l_val << 3) | COMPLEX_SLEW;
writel(regval, base_addr + SCPLL_FSM_CTL_EXT_OFFSET);
writel(SCPLL_NORMAL, base_addr + SCPLL_CTL_OFFSET);
/* Wait for frequency switch to start. */
while (((readl(base_addr + SCPLL_CTL_OFFSET) >> 3) & 0x3F) != l_val)
cpu_relax();
/* Wait for frequency switch to finish. */
while (readl(base_addr + SCPLL_STATUS_OFFSET) & 0x1)
cpu_relax();
}
/* Vote for the L2 speed and return the speed that should be applied. */
static struct clkctl_l2_speed *compute_l2_speed(unsigned int voting_cpu,
struct clkctl_l2_speed *tgt_s)
{
struct clkctl_l2_speed *new_s;
int cpu;
/* Bounds check. */
BUG_ON(tgt_s >= (l2_freq_tbl + l2_freq_tbl_size));
/* Find max L2 speed vote. */
l2_vote[voting_cpu] = tgt_s;
new_s = l2_freq_tbl;
for_each_present_cpu(cpu)
new_s = max(new_s, l2_vote[cpu]);
return new_s;
}
/* Set the L2's clock speed. */
static void set_l2_speed(struct clkctl_l2_speed *tgt_s)
{
if (tgt_s == drv_state.current_l2_speed)
return;
if (drv_state.current_l2_speed->src_sel == 1
&& tgt_s->src_sel == 1)
scpll_change_freq(L2, tgt_s->l_val);
else {
if (tgt_s->src_sel == 1) {
scpll_enable(L2, tgt_s->l_val);
dsb();
select_core_source(L2, tgt_s->src_sel);
} else {
select_core_source(L2, tgt_s->src_sel);
dsb();
scpll_disable(L2);
}
}
drv_state.current_l2_speed = tgt_s;
}
/* Update the bus bandwidth request. */
static void set_bus_bw(unsigned int bw)
{
int ret;
/* Bounds check. */
if (bw >= ARRAY_SIZE(bw_level_tbl)) {
pr_err("%s: invalid bandwidth request (%d)\n", __func__, bw);
return;
}
/* Update bandwidth if requst has changed. */
ret = msm_bus_scale_client_update_request(bus_perf_client, bw);
if (ret)
pr_err("%s: bandwidth request failed (%d)\n", __func__, ret);
return;
}
/* Apply any per-cpu voltage increases. */
static int increase_vdd(int cpu, unsigned int vdd_sc, unsigned int vdd_mem,
unsigned int vdd_dig)
{
int rc = 0;
/* Increase vdd_mem active-set before vdd_dig and vdd_sc.
* vdd_mem should be >= both vdd_sc and vdd_dig. */
rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S0,
rpm_vreg_voter[cpu], vdd_mem, 0);
if (rc) {
pr_err("%s: vdd_mem (cpu%d) increase failed (%d)\n",
__func__, cpu, rc);
return rc;
}
/* Increase vdd_dig active-set vote. */
rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S1,
rpm_vreg_voter[cpu], vdd_dig, 0);
if (rc) {
pr_err("%s: vdd_dig (cpu%d) increase failed (%d)\n",
__func__, cpu, rc);
return rc;
}
/* Update per-core Scorpion voltage. */
rc = regulator_set_voltage(regulator_sc[cpu], vdd_sc, MAX_VDD_SC);
if (rc) {
pr_err("%s: vdd_sc (cpu%d) increase failed (%d)\n",
__func__, cpu, rc);
return rc;
}
return rc;
}
/* Apply any per-cpu voltage decreases. */
static void decrease_vdd(int cpu, unsigned int vdd_sc, unsigned int vdd_mem,
unsigned int vdd_dig)
{
int ret;
/* Update per-core Scorpion voltage. */
ret = regulator_set_voltage(regulator_sc[cpu], vdd_sc, MAX_VDD_SC);
if (ret) {
pr_err("%s: vdd_sc (cpu%d) decrease failed (%d)\n",
__func__, cpu, ret);
return;
}
/* Decrease vdd_dig active-set vote. */
ret = rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S1,
rpm_vreg_voter[cpu], vdd_dig, 0);
if (ret) {
pr_err("%s: vdd_dig (cpu%d) decrease failed (%d)\n",
__func__, cpu, ret);
return;
}
/* Decrease vdd_mem active-set after vdd_dig and vdd_sc.
* vdd_mem should be >= both vdd_sc and vdd_dig. */
ret = rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S0,
rpm_vreg_voter[cpu], vdd_mem, 0);
if (ret) {
pr_err("%s: vdd_mem (cpu%d) decrease failed (%d)\n",
__func__, cpu, ret);
return;
}
}
static void switch_sc_speed(int cpu, struct clkctl_acpu_speed *tgt_s)
{
struct clkctl_acpu_speed *strt_s = drv_state.current_speed[cpu];
if (strt_s->pll != ACPU_SCPLL && tgt_s->pll != ACPU_SCPLL) {
select_clk_source_div(cpu, tgt_s);
/* Select core source because target may be AFAB. */
select_core_source(cpu, tgt_s->core_src_sel);
} else if (strt_s->pll != ACPU_SCPLL && tgt_s->pll == ACPU_SCPLL) {
scpll_enable(cpu, tgt_s->l_val);
dsb();
select_core_source(cpu, tgt_s->core_src_sel);
} else if (strt_s->pll == ACPU_SCPLL && tgt_s->pll != ACPU_SCPLL) {
select_clk_source_div(cpu, tgt_s);
select_core_source(cpu, tgt_s->core_src_sel);
dsb();
scpll_disable(cpu);
} else
scpll_change_freq(cpu, tgt_s->l_val);
/* Update the driver state with the new clock freq */
drv_state.current_speed[cpu] = tgt_s;
}
int acpuclk_set_rate(int cpu, unsigned long rate, enum setrate_reason reason)
{
struct clkctl_acpu_speed *tgt_s, *strt_s;
struct clkctl_l2_speed *tgt_l2;
unsigned int vdd_mem, vdd_dig, pll_vdd_dig;
unsigned long flags;
int rc = 0;
if (cpu > num_possible_cpus()) {
rc = -EINVAL;
goto out;
}
if (reason == SETRATE_CPUFREQ) {
mutex_lock(&drv_state.lock);
#ifdef CONFIG_ACPUCLK_SET_RATE_DEBUG
set_rate_process = current;
mod_timer(&set_rate_timer, jiffies + SETRATE_TIMEOUT);
#endif
}
strt_s = drv_state.current_speed[cpu];
/* Return early if rate didn't change. */
if (rate == strt_s->acpuclk_khz)
goto out;
/* Find target frequency. */
for (tgt_s = acpu_freq_tbl; tgt_s->acpuclk_khz != 0; tgt_s++)
if (tgt_s->acpuclk_khz == rate)
break;
if (tgt_s->acpuclk_khz == 0) {
rc = -EINVAL;
goto out;
}
/* AVS needs SAW_VCTL to be intitialized correctly, before enable,
* and is not initialized at acpuclk_init().
*/
if (reason == SETRATE_CPUFREQ)
AVS_DISABLE(cpu);
/* Calculate vdd_mem and vdd_dig requirements.
* vdd_mem must be >= vdd_sc */
vdd_mem = max(tgt_s->vdd_sc, tgt_s->l2_level->vdd_mem);
/* Factor-in PLL vdd_dig requirements. */
if ((tgt_s->l2_level->khz > SCPLL_LOW_VDD_FMAX) ||
(tgt_s->pll == ACPU_SCPLL
&& tgt_s->acpuclk_khz > SCPLL_LOW_VDD_FMAX))
pll_vdd_dig = SCPLL_NOMINAL_VDD;
else
pll_vdd_dig = SCPLL_LOW_VDD;
vdd_dig = max(tgt_s->l2_level->vdd_dig, pll_vdd_dig);
/* Increase VDD levels if needed. */
if ((reason == SETRATE_CPUFREQ || reason == SETRATE_INIT)
&& (tgt_s->acpuclk_khz > strt_s->acpuclk_khz)) {
rc = increase_vdd(cpu, tgt_s->vdd_sc, vdd_mem, vdd_dig);
if (rc)
goto out;
}
dprintk("Switching from ACPU%d rate %u KHz -> %u KHz\n",
cpu, strt_s->acpuclk_khz, tgt_s->acpuclk_khz);
/* Switch CPU speed. */
switch_sc_speed(cpu, tgt_s);
/* Update the L2 vote and apply the rate change. */
spin_lock_irqsave(&drv_state.l2_lock, flags);
tgt_l2 = compute_l2_speed(cpu, tgt_s->l2_level);
set_l2_speed(tgt_l2);
spin_unlock_irqrestore(&drv_state.l2_lock, flags);
/* Nothing else to do for SWFI. */
if (reason == SETRATE_SWFI)
goto out;
/* Nothing else to do for power collapse. */
if (reason == SETRATE_PC)
goto out;
/* Update bus bandwith request. */
set_bus_bw(tgt_l2->bw_level);
/* Drop VDD levels if we can. */
if (tgt_s->acpuclk_khz < strt_s->acpuclk_khz)
decrease_vdd(cpu, tgt_s->vdd_sc, vdd_mem, vdd_dig);
dprintk("ACPU%d speed change complete\n", cpu);
/* Re-enable AVS */
if (reason == SETRATE_CPUFREQ)
AVS_ENABLE(cpu, tgt_s->avsdscr_setting);
out:
if (reason == SETRATE_CPUFREQ) {
mutex_unlock(&drv_state.lock);
#ifdef CONFIG_ACPUCLK_SET_RATE_DEBUG
del_timer(&set_rate_timer);
#endif
}
return rc;
}
static void __init scpll_init(int sc_pll)
{
uint32_t regval;
dprintk("Initializing SCPLL%d\n", sc_pll);
/* Clear calibration LUT registers containing max frequency entry.
* LUT registers are only writeable in debug mode. */
writel(SCPLL_DEBUG_FULL, sc_pll_base[sc_pll] + SCPLL_DEBUG_OFFSET);
writel(0x0, sc_pll_base[sc_pll] + SCPLL_LUT_A_HW_MAX);
writel(SCPLL_DEBUG_NONE, sc_pll_base[sc_pll] + SCPLL_DEBUG_OFFSET);
/* Power-up SCPLL into standby mode. */
writel(SCPLL_STANDBY, sc_pll_base[sc_pll] + SCPLL_CTL_OFFSET);
dsb();
udelay(10);
/* Calibrate the SCPLL to the maximum range supported by the h/w. We
* might not use the full range of calibrated frequencies, but this
* simplifies changes required for future increases in max CPU freq.
*/
regval = (L_VAL_SCPLL_CAL_MAX << 24) | (L_VAL_SCPLL_CAL_MIN << 16);
writel(regval, sc_pll_base[sc_pll] + SCPLL_CAL_OFFSET);
/* Start calibration */
writel(SCPLL_FULL_CAL, sc_pll_base[sc_pll] + SCPLL_CTL_OFFSET);
/* Wait for proof that calibration has started before checking the
* 'calibration done' bit in the status register. Waiting for the
* LUT register we cleared to contain data accomplishes this.
* This is required since the 'calibration done' bit takes time to
* transition from 'done' to 'not done' when starting a calibration.
*/
while (readl(sc_pll_base[sc_pll] + SCPLL_LUT_A_HW_MAX) == 0)
cpu_relax();
/* Wait for calibration to complete. */
while (readl(sc_pll_base[sc_pll] + SCPLL_STATUS_OFFSET) & 0x2)
cpu_relax();
/* Power-down SCPLL. */
scpll_disable(sc_pll);
}
/* Force ACPU core and L2 cache clocks to rates that don't require SCPLLs. */
static void __init unselect_scplls(void)
{
int cpu;
/* Ensure CAL_IDX frequency uses AFAB sources for CPU cores and L2. */
BUG_ON(acpu_freq_tbl[CAL_IDX].core_src_sel != 0);
BUG_ON(acpu_freq_tbl[CAL_IDX].l2_level->src_sel != 0);
for_each_possible_cpu(cpu) {
select_clk_source_div(cpu, &acpu_freq_tbl[CAL_IDX]);
select_core_source(cpu, acpu_freq_tbl[CAL_IDX].core_src_sel);
drv_state.current_speed[cpu] = &acpu_freq_tbl[CAL_IDX];
l2_vote[cpu] = acpu_freq_tbl[CAL_IDX].l2_level;
}
select_core_source(L2, acpu_freq_tbl[CAL_IDX].l2_level->src_sel);
drv_state.current_l2_speed = acpu_freq_tbl[CAL_IDX].l2_level;
}
/* Ensure SCPLLs use the 27MHz PXO. */
static void __init scpll_set_refs(void)
{
int cpu;
uint32_t regval;
/* Bit 4 = 0:PXO, 1:MXO. */
for_each_possible_cpu(cpu) {
regval = readl(sc_pll_base[cpu] + SCPLL_CFG_OFFSET);
regval &= ~BIT(4);
writel(regval, sc_pll_base[cpu] + SCPLL_CFG_OFFSET);
}
regval = readl(sc_pll_base[L2] + SCPLL_CFG_OFFSET);
regval &= ~BIT(4);
writel(regval, sc_pll_base[L2] + SCPLL_CFG_OFFSET);
}
/* Voltage regulator initialization. */
static void __init regulator_init(void)
{
struct clkctl_acpu_speed **freq = drv_state.current_speed;
const char *regulator_sc_name[] = {"8901_s0", "8901_s1"};
int cpu, ret;
for_each_possible_cpu(cpu) {
/* VDD_SC0, VDD_SC1 */
regulator_sc[cpu] = regulator_get(NULL, regulator_sc_name[cpu]);
if (IS_ERR(regulator_sc[cpu]))
goto err;
ret = regulator_set_voltage(regulator_sc[cpu],
freq[cpu]->vdd_sc, MAX_VDD_SC);
if (ret)
goto err;
ret = regulator_enable(regulator_sc[cpu]);
if (ret)
goto err;
}
return;
err:
pr_err("%s: Failed to initialize voltage regulators\n", __func__);
BUG();
}
/* Register with bus driver. */
static void __init bus_init(void)
{
bus_perf_client = msm_bus_scale_register_client(&bus_client_pdata);
if (!bus_perf_client) {
pr_err("%s: unable register bus client\n", __func__);
BUG();
}
}
#ifdef CONFIG_CPU_FREQ_MSM
static struct cpufreq_frequency_table freq_table[NR_CPUS][20];
static void __init cpufreq_table_init(void)
{
int cpu;
for_each_possible_cpu(cpu) {
int i, freq_cnt = 0;
/* Construct the freq_table tables from acpu_freq_tbl. */
for (i = 0; acpu_freq_tbl[i].acpuclk_khz != 0
&& freq_cnt < ARRAY_SIZE(*freq_table); i++) {
if (acpu_freq_tbl[i].use_for_scaling[cpu]) {
freq_table[cpu][freq_cnt].index = freq_cnt;
freq_table[cpu][freq_cnt].frequency
= acpu_freq_tbl[i].acpuclk_khz;
freq_cnt++;
}
}
/* freq_table not big enough to store all usable freqs. */
BUG_ON(acpu_freq_tbl[i].acpuclk_khz != 0);
freq_table[cpu][freq_cnt].index = freq_cnt;
freq_table[cpu][freq_cnt].frequency = CPUFREQ_TABLE_END;
pr_info("CPU%d: %d scaling frequencies supported.\n",
cpu, freq_cnt);
/* Register table with CPUFreq. */
cpufreq_frequency_table_get_attr(freq_table[cpu], cpu);
}
}
#else
static void __init cpufreq_table_init(void) {}
#endif
static unsigned int __init select_freq_plan(void)
{
uint32_t raw_speed_bin, speed_bin, max_khz;
struct clkctl_acpu_speed *f;
acpu_freq_tbl = acpu_freq_tbl_v2;
l2_freq_tbl = l2_freq_tbl_v2;
l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl_v2);
raw_speed_bin = readl(QFPROM_SPEED_BIN_ADDR);
speed_bin = raw_speed_bin & 0xF;
if (speed_bin == 0xF)
speed_bin = (raw_speed_bin >> 4) & 0xF;
if (speed_bin == 0x1)
max_khz = 1512000;
else
max_khz = 1188000;
/* Truncate the table based to max_khz. */
for (f = acpu_freq_tbl; f->acpuclk_khz != 0; f++) {
if (f->acpuclk_khz > max_khz) {
f->acpuclk_khz = 0;
break;
}
}
f--;
pr_info("Max ACPU freq: %u KHz\n", f->acpuclk_khz);
return f->acpuclk_khz;
}
void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
{
unsigned int max_cpu_khz;
int cpu;
mutex_init(&drv_state.lock);
spin_lock_init(&drv_state.l2_lock);
drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
/* Configure hardware. */
max_cpu_khz = select_freq_plan();
unselect_scplls();
scpll_set_refs();
for_each_possible_cpu(cpu)
scpll_init(cpu);
scpll_init(L2);
regulator_init();
bus_init();
/* Improve boot time by ramping up CPUs immediately. */
for_each_online_cpu(cpu)
acpuclk_set_rate(cpu, max_cpu_khz, SETRATE_INIT);
cpufreq_table_init();
}
Realize that this is my first modification so there might be some mistakes...
I would recommend you scroll up slowly from the bottom and look for the if/else statement that still limits you to 1.2
Also, check your math on max voltages available to the clock speed at 1.5 - I know it'll work, but you are a bit undervolted for proper operation. Not too big a deal, but might lead to losing information from RAM if left unchecked and not changed elsewhere. (unless you are shooting for an undervolt kernel - but then you'd have to re-scale the rest of the voltages down the line)
Don't forget to crawl through the rest of the kernel code on the hardware side and make sure there aren't any other limiters preventing your change from taking place - board-doubleshot.c is another place you will find 1.2 limiters enacted combined with voltage regulation.
I am hesitant to lay out a how-to on this, because it's very easy to melt your chip if not careful, or fry the RAM or GPU if you don't do your math right for voltage regulation across the mainboard. Also because teaching math is something i'm not very good at and get frustrated easily trying to do.
Explaining how to do math for processor scaling is way beyond my abilities for providing here, so google becomes your friend and a lot of math workshops are in your near future if you want to get into doing this.
I would also spend some time reading up on dual-core theory and the principles behind preventing both cores from trying to steal each others work.
Since the info is sitting right here for anyone who wants to download kernel source and give it a shot, just please, make sure you know what you are doing when you start messing with voltages or you will break your phone on a hardware level. Melting your processor or frying your RAM is no fun.
Releasing an overclock kernel to the community that has not been thoroughly tested without very clearly stating so is negligent, so please, please make sure you aren't frying people's phones before pushing ahead with something like this publicly. (general statement for anyone reading this)
I am glad to see other people getting into this, cautionary words aside, and look forward to what people come up with.

[Kernel] Neok AceDroid V1.1 OC/UV/2012-Feb-06 | Amazing Smooth, Super Battery

This kernel is base on LeeDroid Kernel source
Neok AceDroid Kernel for Sense ROMS
Amazing Smooth Working!!! and Amazing battery efficiency
Changelog
- CFS Kernel
- Add TINY_PREEMPT_RCU
- Add RCU Booster
- Apply RCU Optimization
- Add SIO I/O Scheduler with SIO tweak
- 2.6.36 kernel Ondemand CPU Governor
- Add SmartasV2 CPU Governor
- Apply Smooth and higher battery efficiency tweak for SmartasV2
- Optimize CPU Clock table
- CFS tweak
- Disabled Sched-GENTLE_FAIR_SLEEPERS
- Apply AXI (Good for battery)
- improve SDHC card stability
- Compiled by Linaro GCC4.5.4 (2011.08)
- Apply compile optimze FLAG
- Update MSM3.0 kernel's Wlan driver by LorDClockaN
Changlog as 1.0 to 1.1 Version
- Remove popping noise sound by LorDClockaN
- Fix CPUFreq table fix
- min CPUFreq change 122 -> 230
- Fixed ext4 disk write performance regression
- Add genlock and msm related changes by LorDClokaN
- msm: cpufreq: Improve initial frequency selection - CodeAurora
- change compile optimization flag
Default kernel cpu setting
CPU Governor - SmartassV2
Max clock -1036Mhz
Min clock -230Mhz
Compile optimze FLAG
-mtune=cortex-a8 -march=armv7-a -mfpu=neon -mfloat-abi=hard \
-fsingle-precision-constant -ftree-vectorize -funswitch-loops \
-fforce-addr -fprofile-correction -falign-loops \
-fpredictive-commoning -fgcse-after-reload -pipe
Kernel CPU Clock table
static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 24576, SRC_LPXO, 0, 0, 30720, 900, VDD_RAW(900) },
{ 61440, PLL_3, 5, 11, 61440, 900, VDD_RAW(900) },
{ 122880, PLL_3, 5, 5, 61440, 900, VDD_RAW(900) },
{ 184320, PLL_3, 5, 4, 61440, 900, VDD_RAW(900) },
{ MAX_AXI_KHZ, SRC_AXI, 1, 0, 61440, 900, VDD_RAW(900) },
{ 122000, PLL_3, 5, 2, 61440, 875, VDD_RAW(875) },
{ 230400, PLL_3, 5, 1, 192000, 900, VDD_RAW(900) },
{ 307200, PLL_3, 5, 1, 192000, 900, VDD_RAW(900) },
{ 422400, PLL_3, 5, 1, 192000, 925, VDD_RAW(925) },
{ 499200, PLL_1, 2, 0, 192000, 950, VDD_RAW(950) },
{ 652800, PLL_2, 3, 0, 192000, 1000, VDD_RAW(1000) },
{ 729600, PLL_2, 3, 0, 192000, 1000, VDD_RAW(1000) },
{ 806400, PLL_2, 3, 0, 192000, 1025, VDD_RAW(1025) },
{ 883200, PLL_2, 3, 0, 192000, 1050, VDD_RAW(1050) },
{ 960000, PLL_2, 3, 0, 192000, 1050, VDD_RAW(1050) },
{ 998400, PLL_2, 3, 0, 192000, 1050, VDD_RAW(1050) },
{ 1036800, PLL_2, 3, 0, 192000, 1075, VDD_RAW(1075) },
{ 1113600, PLL_2, 3, 0, 192000, 1100, VDD_RAW(1100) },
{ 1190400, PLL_2, 3, 0, 192000, 1125, VDD_RAW(1125) },
{ 1267200, PLL_2, 3, 0, 192000, 1150, VDD_RAW(1150) },
{ 1344000, PLL_2, 3, 0, 192000, 1175, VDD_RAW(1175) },
{ 1420800, PLL_2, 3, 0, 192000, 1200, VDD_RAW(1200) },
{ 1497600, PLL_2, 3, 0, 192000, 1275, VDD_RAW(1275) },
{ 1536000, PLL_2, 3, 0, 192000, 1300, VDD_RAW(1300) },
{ 1612800, PLL_2, 3, 0, 192000, 1350, VDD_RAW(1350) },
{ 1689600, PLL_2, 3, 0, 192000, 1375, VDD_RAW(1375) },
{ 1766400, PLL_2, 3, 0, 192000, 1425, VDD_RAW(1425) },
{ 1843200, PLL_2, 3, 0, 192000, 1450, VDD_RAW(1450) },
Kernel Source - https://github.com/kgp700/
Thanks to LeeDroid and LorD ClockaN
Is this for Sense Rom?
Yes, its for sense roms
Sent from my Desire HD using XDA App
inzaghi75 said:
Is this for Sense Rom?
Click to expand...
Click to collapse
yes for sense roms
kgp700 said:
yes for sense roms
Click to expand...
Click to collapse
will try this beast
Has it uv? Is the Best to use daemon or setcpu?
Inviato dal mio Desire HD usando Tapatalk
Currently running the v1.0 on the ER3BUSXL3.5 and it's pretty smooth working till now. Thanks for the work
USB D/C
What about USB D/C when the top bar is pulled down or WiFi is on/off operated?
Just flash on ER3BUSXL3.6
Ty
devilrex said:
Just flash on ER3BUSXL3.6
Ty
Click to expand...
Click to collapse
Very helpful post. This means two things:
1) Kernel is sense designed (which Op already stated);
2) You learned how to flash a kernel.
whiperhack said:
Very helpful post. This means two things:
1) Kernel is sense designed (which Op already stated);
2) You learned how to flash a kernel.
Click to expand...
Click to collapse
And you learned how to write a post
thanks for your new kernel .good work ...
Hum with smartassV2 my phone freez with 1.5GHz lol but with lord or rcmix kernel i can put 1.7GHz or 1.68GHz in Ondemand
hi!
hello kernel another kernel dev!
looking at your changelog all I can say it's the same as mine sense kernel but with little less features
mattiadj said:
Has it uv? Is the Best to use daemon or setcpu?
Inviato dal mio Desire HD usando Tapatalk
Click to expand...
Click to collapse
yes it support undervolt
i like setcpu
unhallowedone said:
Currently running the v1.0 on the ER3BUSXL3.5 and it's pretty smooth working till now. Thanks for the work
Click to expand...
Click to collapse
thanks
whiperhack said:
What about USB D/C when the top bar is pulled down or WiFi is on/off operated?
Click to expand...
Click to collapse
no problem
devilrex said:
Just flash on ER3BUSXL3.6
Ty
Click to expand...
Click to collapse
thanks
kgp700 said:
Strongly Recommand Wipe dalvik cache after kernel update!!!
Click to expand...
Click to collapse
In fact, dalvik cache has nothing to do with kernel, so wiping it isn't really necessary
brolee93 said:
thanks for your new kernel .good work ...
Hum with smartassV2 my phone freez with 1.5GHz lol but with lord or rcmix kernel i can put 1.7GHz or 1.68GHz in Ondemand
Click to expand...
Click to collapse
i'm tested about that
no problem on 1.5Ghz, SmartassV2
But have freeze on 1.6Ghz or higher clock with smartassv2
no problem on 1.7Ghz, ondemand governor
if you want use high cpu clock, i recommand ondemand governor
but not recommand high cpu overclock
LorD ClockaN said:
hi!
hello kernel another kernel dev!
looking at your changelog all I can say it's the same as mine sense kernel but with little less features
Click to expand...
Click to collapse
hi
thanks for reply
and thanks kernel source
yes less features than your kernel
i need some study for kernel
if you possible,
use my kernel, then please assessment about my kernel
(sorry my bad english)
sigurd_LU said:
In fact, dalvik cache has nothing to do with kernel, so wiping it isn't really necessary
Click to expand...
Click to collapse
ok thanks
ths guy，
i try the kernel，
and found there is A little noise when play music。
As latest RCMiX kernel there is a little background noise after any sound...
framir said:
As latest RCMiX kernel there is a little background noise after any sound...
Click to expand...
Click to collapse
+1
yes，all kernel have noise except LorDmoD kernel。
abaochen said:
+1
yes，all kernel have noise except LorDmoD kernel。
Click to expand...
Click to collapse
Please remove this fastidious noise!

[HACK] Overclocking and tuning Adreno200 GPU & misc qsd8k development

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"Hey Dev! Make those Snapdragons fly!"​
A little into:
Hello wonderful and amazing people! I'm Fera, ROM/Kernel developer from SonyXperia X10 forum. I'm 20 years old hungry student and I'd like to share a bit of my experience with you guys. Open Source rules! :highfive: Hacks listed here have to work despite kernel versions. I made this hacks specificly for qsd8k board, but you may try your luck on newer chipsets if you get the logic. Things are pretty similar on Snapdragon chipsets. I spent a lot of hard time figuring things out so if you like this stuff, hit 'Thanks' button, rate this thread, share it to let other people know, and feed me.
Now..enough for drama, have good music, tighten your belts, sit back and relax - we're going to fly at the speed of light..
GPU and CPU overclocking:
I will show an example by overclocking my Sony Ericsson Xperia X10 retired phone with QSD8x50 Snapdragon S1 board with Adreno200 rev1 GPU onboard. You may look at more complex details list of Adreno GPU HERE.
Let's start now. This hack requiers to recompile kernel for your device. It's quite simple actually. To keep things more clear, let's note what we have:
Code:
grp_clock = Graphics clock //128000000 by default for adreno200 rev1
ebi1_clock = External Bus Interface 1 clock //256000000 by default for qsd8k
imem_clock = Internal Graphics Memory clock //256000000 by default for qsd8k
We're going to deal with grp_clock of Adreno bus clock and CPU clock itself.
In kernel sources under arch/arm/mach-msm we have acpuclock-8x50.c file. This file (or any equivalent to your board) contains actual CPU freq. table and misc hw stuff related to clocks.
Default freq. table for qsd8k is:
PHP:
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1025},
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1200},
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1225},
{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1275},
{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1275},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
Little theory lesson:
Let's take last line and digest it..
1/0 - means that this clk ladder is enabled/disabled
998400 - Actual ladder freq. in Khz
ACPU_PLL_3, 0, 0, 0, 0 - AXI/PLL macros, adresses
128000 - AXI bus freq. in Khz
0/1/2 - Init adresses
0x1A - Step raw code for CPU
1300 - Voltage gained to corresponding freq. step in mV
We can see that we have 128000 freq. on top of the table set as 0 (disabled) for global access and reserved for PLL_1 which is adressed to 2. After hardcore testings I found out that this adresses to GPU AXI bus clock used by Adreno200. We simply change it to 192000Khz. Overclocking to higher values made my device very unstable, so don't bump high too much.
The ready line will be look as:
PHP:
{ 0, 192000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000 },
But it's not all. Note that this may vary in your .c file so turn on your brain and search for axi defines. In my case it was in same .c file in this function :
Code:
unsigned long clk_get_max_axi_khz(void)
{
return 128000;
}
EXPORT_SYMBOL(clk_get_max_axi_khz);
Find something similar to this (if it realy exists) and set value to 192000.
Now we have to update all CPU freq table with overclocked axi bus values which could be stable.. At this point I spent monthes of testing and finally came up to stable things. I will just paste here my table which also includes CPU overclock and undervolt:
PHP:
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000 },
{ 0, 192000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000 },
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1025 },
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1025 },
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1025 },
{ 1, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1025 },
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1025 },
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1025 },
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1025 },
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1050 },
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1075 },
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1100 },
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x13, 1125 },
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1125 },
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1150 },
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1200 },
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 160000, 1, 0x17, 1225 },
{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 160000, 1, 0x18, 1250 },
{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 160000, 1, 0x19, 1275 },
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 192000, 1, 0x1A, 1300 },
{ 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 192000, 1, 0x1B, 1325 },
{ 1, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 192000, 1, 0x1C, 1325 },
{ 1, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 192000, 1, 0x1D, 1325 },
{ 1, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 192000, 1, 0x1E, 1350 },
{ 1, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 192000, 1, 0x1F, 1350 },
{ 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 192000, 1, 0x20, 1375 },
{ 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 192000, 1, 0x21, 1425 },
{ 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 192000, 1, 0x22, 1425 },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
This is how my table looks after GPU/CPU overclock/undervolt and hard testings. I find theese values solid stable and best at performance, exept last freq ladder. 1.3Ghz overclock is a bit overdose for my device (since it is max available freq. ladder for my cpu) but I save it in case there is a phone of mine with balls of steel (not all CPU chips are same and not all can handle overclocking). As you may notice, overclocked axi frequency is enabled on higher CPU clock steps. This means that axi overclock will be enabled when CPU runs on 1113Mhz and higher, so to enable all this things you have to use overclocked CPU table.
Since we overclocked our CPU we need to modify our .c file with all theese tables furter (acpuclock-8x50.c in my case) to match new changes. Search for:
Code:
case 0x00:
max_acpu_khz = 998400;
and set it to 1305600 (maximum available CPU freq.)
Then searching for this:
Code:
static struct cpufreq_frequency_table freq_table[20];
and changing the value in the ind to 28 since we have now 28 CPU freq. steps in total. That's all for CPU overclock. Continuing boosting our Adreno..
Open your board-****.c file.
If you use old KGSL drivers (Android 2.3 and older), search for struct kgsl_platform_data kgsl_pdata function. In function structure you will see this:
Code:
.high_axi_3d = 128000,
.max_grp3d_freq = 0,
.min_grp3d_freq = 0,
Set high_axi_3d value to 192000.
Set max_grp3d_freq value to 256*1000*1000.
Set min_grp3d_freq value to 192*1000*1000.
If you use new KGSL drivers (Android 4.0+) then search for struct kgsl_device_platform_data kgsl_3d0_pdata. You will see something like this:
PHP:
.pwrlevel = {
{
.gpu_freq = 0,
.bus_freq = 128000000,
},
Set gpu_freq value to 256000000.
Set bus_freq value to 192000000.
In the end we have undervolted and overclocked (1.3Ghz) CPU and overclocked GPU of my old phone. Saying again..Overclocking bus higher than 192Khz is realy bad idea for QSD8x50.
When you're done, build your kernel with enabled debugging (CONFIG_DEBUG_KERNEL=y) and then add this script to mount debug sysfs dir. in init.d or anywhere else on auostart:
Code:
#!/system/bin/sh
### FeraLab ###
mount -t debugfs debugfs /sys/kernel/debug
echo 0 > /sys/kernel/debug/msm_fb/0/vsync_enable
This script will also disable VSYNC to boost your 2D FPS. When system runs check out /sys/kernel/debug/clk_rate folder (If you can't see this folder the your init.d support is not working properly..put script somewhere else, in /etc/hw_config.sh for ex.). You will have to see reports:
gp_clk - 192000000
grp_3d_clk - 256000000
imem_clk - 256000000
And for CPU overclocking use any app you like from market. No-frill-CPU is a good one.
Bingo! :silly:
Now I can play such games like NFS MW or GTA Vice City on my retired but rocking phone.. (proof video)
If you like this - feed me :good:
Display panel overclocking:
Still not enough? Wow..you're d thirsty one..
Ok.. Let's overclock your LCD bus frequency then..
Install any app on you pc that could recursively search txt from kernel directory (I use double-cmd-gtk on ubuntu) or just search you git repo online. Fins this thing (It may vary on 3.x kernels. This is for 2.6 ones):
Code:
panel_info.clk_rate
This part of code will most probably be under /drivers/video/msm folder or directly in your board-xxx.c file which is just my case.
I have this values by default:
Code:
panel_data->panel_info.clk_rate = 192000000;
panel_data->panel_info.clk_min = 190000000;
panel_data->panel_info.clk_max = 200000000;
Simply change to
Code:
panel_data->panel_info.clk_rate = 235000000;
panel_data->panel_info.clk_min = 192000000;
panel_data->panel_info.clk_max = 256000000;
Done :good:
Updating KGSL drivers in kernel:
At first I though this is realy hard to do but I dealed with this and wanna show you a quick and easy way to do it. It is pretty same for most kernel versions. I will do an example using my 2.6 kernel.
Basicly, just get my sourcecode .zip, extract it somewhere. Go to your kernel's /drivers/gpu/msm (or drivers/char/msm) folder and delete it. Now go to my kernel/drivers/gpu/msm and copy that folder to your kernel. Not finished yet. Replace your file with mine from my kernel/include/linux/msm_kgsl.h. Done. Yeah. Soo simple. This are latest CAF gb_release KGSL drivers which improved my 3D performance around 30%. Don't forget to update ROM libs. (You may take them from my .zip too) Same thing is for newer android versions, but dont copy it from my kernel. My kernel is for GingerBread atm.
Tuning Adreno GPU:
This is more simple than previos guides and is already familiar, but I will stick it here again anyway.
It's about using Adreno config file. This will work only on GingerBread ROMs. To make it working place this part of code in your /system/etc/hw_config.sh:
Code:
if [ ! -h /data/local/tmp/adreno_config.txt ]; then
chmod 777 /system/etc/adreno_config.txt
ln -s /system/etc/adreno_config.txt /data/local/tmp/adreno_config.txt
fi
Now edit and put your adreno_config.txt in /system/etc/ and set all permissions for it (chmod 777). Also edit your build.prop, add:
Code:
debug.egl.hw=1
debug.egl.profiler=1
debug.performance.tuning=1
debug.sf.hw=1
This is how originnal version of adreno_config file looks like. It contains various explanations and I will put it here so you could refer to.
Now what parameters are realy cool to tune are:
Code:
forceAutoTextureCompression=1
triJuice=3
Theese configs have to greatly improve your 3D performance in cost of quality, but I think it doesnt matter anymore for old devices.
Juice it:
A simple trick to disable framebuffer swapping and flush all frames without filtering os to edit your build.prop and add/replace theese strings:
Code:
debug.sf.hw=1
debug.egl.hw=1
debug.egl.profiler=1
debug.performance.tuning=1
debug.gr.swapinterval=0
debug.egl.swapinterval=0
This will double your 2D FPS but you will get UI glithces instead. It's not because something've get slow - it's because it've get too fast . If you wish to use this trick for prolonged use, I suggest you do disable all animations in system settings.
Probably you may want have a look at another my thread for optimized apps & games HERE.
I think that's it for now. Have a nice day-time. Peace out! :fingers-crossed:
tuning adreno gpu
while i wanted to try this hack however i find it impossible as my phone htc hd2 has not got a hw_config.sh in it searched with es file explorer and root explorer and also in system etc and cant find the file. is there any other way to do this? cant do kernel hack as no nothing about kernels at all phone htc hd2 cm7 gingerbread rom http://forum.xda-developers.com/showthread.php?t=1867986 it is fast and very stable but would be nice to tweak it a bit. Oh and for juice it in my build prop only have debug.sf.hw=1 not the other debug lines do i just add them to build.prop. thank you
Well i ain't pro in kernel developing but is it work with adreno 205-8255 chipset-mogami board?
yamin8000 said:
Well i ain't pro in kernel developing but is it work with adreno 205-8255 chipset-mogami board?
Click to expand...
Click to collapse
Yes, adreno 205 has been overclocked before. See this commit: https://github.com/Evervolv/android...mmit/9d5bda971744f536125488a19043b0003bbbfd73
yamin8000 said:
Well i ain't pro in kernel developing but is it work with adreno 205-8255 chipset-mogami board?
Click to expand...
Click to collapse
npz said:
Yes, adreno 205 has been overclocked before. See this commit: https://github.com/Evervolv/android...mmit/9d5bda971744f536125488a19043b0003bbbfd73
Click to expand...
Click to collapse
I realy hope that that commit realy does overclock andreno205, because in adreno200, despite of setting various values for same kgsl-3d data function, grp_clk was still reporting same default value.. Thats why i digged deeper to find out how adrenos work.. I dont know how do new chips work but older ones frequencies are fully depended on cpu..
antutu benchmark score would be nice to compare the results before & after cpu and gpu OC each :3
Flaîm said:
antutu benchmark score would be nice to compare the results before & after cpu and gpu OC each :3
Click to expand...
Click to collapse
I will say about my kernel..that after all optimizations of my kernel..which are not only overclocking, comparing quadrant 3d scores..60% improvement was observed. Comparing cpu score on antutu.. 80% of improvement was observed. Not many dual core cpus can reach 1400 in antutu cpu.. I get it on my one core. Overall my kernel does roughly double higher score than stock firmware. I will attach screensjots later.
@FeraVolt Can you please help me to overclock my GPU on MSM7225A? The kernel source is here: https://github.com/rootdefyxt320/android_kernel_motorola_tinboost My kernel version is 2.6.38.6
EDIT: Okay, here is my acpuclock-7201.c:
Code:
/* 7x25a pll2 at 1200mhz with GSM capable modem */
static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_800_25a[] = {
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
{ 0, 61440, ACPU_PLL_1, 1, 3, 7680, 3, 1, 61440 },
{ 1, 122880, ACPU_PLL_1, 1, 1, 15360, 3, 2, 61440 },
{ 1, 245760, ACPU_PLL_1, 1, 0, 30720, 3, 3, 61440 },
{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 150000 },
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
{ 0, 400000, ACPU_PLL_4, 6, 1, 50000, 3, 4, 122880 },
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 200000 },
May you please help me to interpret it?
HTC HD2
Would this hack work on an old HTC HD2 , it has Adreno 200 (AMD Z430) with OpenGL ES 2.0 support GPU and a Snapdragon S1 QSD8250 chipset
EvilMegaDroid said:
Would this hack work on an old HTC HD2 , it has Adreno 200 (AMD Z430) with OpenGL ES 2.0 support GPU and a Snapdragon S1 QSD8250 chipset
Click to expand...
Click to collapse
Yes
Sent from my X10i using XDA Free mobile app
Can't find
I can't find the board-****.c file
Will this work on adreno 203...on arubaslim board on my Samsung galaxy core duos.snapdragon s4 play???
Thread updated with newer CPU freq table for qsd8k. True 1,3Ghz overclock...
Another update in OP. New CPU freq. table, and improved board-config fine-tuning.
So I'm guessing I cannot pull the kernel from my phone decompile edit some stuff and then recompile....bummer
Sent from my LT28i using XDA Free mobile app
You can compile kernel from source code only
Sent from my X10i using xda premium
Hi, how i change minimum and max CPU clock on i9515 stock ROM?
lorenzitto said:
Hi, how i change minimum and max CPU clock on i9515 stock ROM?
Click to expand...
Click to collapse
On new devices sysfs can be used for this reason. Otherwise kernel recompilation is required
How I can do it on the cyanogenmod 12.1 ported for i9515 ( s4 4g ) ?
It depends on your kernel

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